Meta’s AI Infrastructure Shifts to Google Chips
A new PyTorch-native engine allows Meta to run production AI workloads on Google's TPUs, challenging Nvidia's hardware dominance.
By Fatima Zayed ·

The rigid software ecosystem that has long defined high-performance artificial intelligence computing is cracking. For years, the industry standard for running large language models relied heavily on a specific combination of hardware and software frameworks, creating a barrier to entry for companies seeking alternatives. Now, that barrier has been breached. Google has announced that its custom Tensor Processing Units (TPUs) are officially serving AI workloads in production at Meta, the creator of the PyTorch framework. This move marks a significant departure from the status quo, as it provides a native pathway for PyTorch developers to utilize Google’s silicon without the need for extensive code rewrites.
The technical foundation of this shift is a new version of the SGLang inference engine, alongside an open-source release of vLLM. Previously, running these engines on TPUs required developers to use Google’s JAX framework. The new updates allow TPUs to function as a native option within the PyTorch ecosystem. Zongwei Zhou, Meta’s lead for PyTorch-TPU, confirmed that the SGLang-TorchTPU system is already live in production at Meta. He described the achievement as the result of a close three-way collaboration between Meta, Google, and the SGLang team, noting that it provides Meta with a remarkably mature serving stack.
Meta’s motivation is driven by a strategic desire for hardware independence. Jana van Greunen, director of PyTorch engineering at Meta, stated that the company cannot be constrained by a single hardware architecture. By adopting the new TorchTPU backend, Meta can deploy its PyTorch workloads directly onto Google’s hardware. Google confirmed that it co-developed this technology with Meta’s PyTorch team, signaling a deeper technical partnership between the two tech giants.
This is not the first time the two companies have intersected on this hardware. Google identifies its older PyTorch/XLA bridge as a predecessor to the current TorchTPU system. Reports from SemiAnalysis indicated that Meta research teams utilized TPUs through this older bridge between 2020 and 2023, a period that ended when Meta canceled those specific contracts. The new push appears specifically targeted at Meta, which had previously resisted migrating its core infrastructure to the JAX framework.
The physical location of these production TPUs remains unspecified, though industry talks from last year suggested a timeline of Google Cloud TPU rentals in 2026 followed by direct purchases in 2027. Meta is reportedly in a multi-year rental agreement, cementing the hardware arrangement. The announcement landed just one day after Amazon open-sourced TorchNeuron, its own native PyTorch backend for Trainium chips, suggesting a coordinated industry effort to loosen the software lock-in traditionally associated with Nvidia.
Performance metrics underscore the viability of this new configuration. A tuned vLLM setup serving the 2.8-trillion-parameter Kimi K3 model reportedly exceeds 700 tokens per second for a single user on the seventh-generation Ironwood TPU. This benchmark was conducted by Inferact, a startup founded by vLLM’s creators, which assisted in building the new engine. The test utilized 16 Ironwood chips with speculative decoding, outpacing a comparable setup on 16 Nvidia GB200s that achieved 452 tokens per second. Without speculative decoding, the new kernels deliver roughly 1.4 to 2 times the throughput of the GB200 baseline at small batch sizes.
Looking ahead, the ecosystem is poised for rapid expansion. SGLang-TorchTPU will begin adding support for new models, starting with DeepSeek V4.1 Flash and Reflection Beam. RadixArk aims to achieve Day 0 TPU support for new open models by the first quarter of 2027, ensuring that new releases are supported immediately. Google, Meta, and RadixArk are scheduled to share further details at the SGLang Summit in San Francisco in November 2026.
Source: Tom's Hardware





